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features description applications ads1225 ads1226 sbas346 ? may 2006 24-bit analog-to-digital converter with one- and two-channel differential inputs and internal oscillator 100sps data rate (high-speed mode) the ads1225 and ads1226 are 24-bit delta-sigma analog-to-digital (a/d) converters. they offer single-cycle settling excellent performance, ease-of-use, and low power easy conversion control with start pin in a small 4mm 4mm qfn package and are automatic shutdown well-suited for demanding high-resolution low noise: 4 m v rms noise (high-resolution measurements, especially in portable and other space-saving and power-constrained applications. mode) input multiplexer with two differential the ads1225 and ads1226 convert on command channels (ads1226) using a dedicated start pin. simply pulse this pin to initiate a conversion. data is read in a single cycle voltage reference supports ratiometric for retrieval over a 2-wire serial interface that easily measurements connects to popular microcontrollers like the self-calibrating msp430. after the conversion completes, the simple read-only 2-wire serial interface ads1225 and ads1226 automatically shuts down all circuitry. internal high-impedance input buffer internal features include a two-channel multiplexer internal temperature sensor (ads1226), selectable input buffer, temperature internal oscillator sensor, and oscillator. the full-scale range is defined low-power: 1mw while operating, < 1 m a by the external voltage reference with support during shutdown provided for up to a 5v differential input signal. two operating modes allow for speed (100sps data rate, analog and digital supplies: 2.7v to 5.5v 15 m v rms noise) or resolution (4 m v rms noise, 16sps data rate). hand-held instrumentation the ads1225/6 supports 2.7 to 5.5v analog and digital supplies. power consumption is 1mw while portable medical equipment converting with 3v supplies. the ads1225 and industrial process control ads1226 are fully specified over an extended industrial temperature range of ?40 c to +105 c. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. all trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2006, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. ads1225 ads1226
mux serial interface ds adc vrefp vrefn buffer avdd dvdd gnd mux ads1226 only ainp1 ainn1 ainp2 ainn2 drdy/dout sclk tempen start oscillator mode bufen
ordering information absolute maximum ratings ads1225 ads1226 sbas346 ? may 2006 this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. for the most current package and ordering information, see the package option addendum located at the end of this data sheet or see the ti web site at www.ti.com. over operating free-air temperature range (unless otherwise noted) (1) ads1225, ads1226 unit avdd to gnd ?0.3 to +6 v dvdd to gnd ?0.3 to +6 v 100, momentary ma input current 10, continuous ma analog input voltage to gnd ?0.3 to avdd +0.3 v digital input voltage to gnd ?0.3 to to avdd +0.3 v maximum junction temperature +150 c operating temperature range ?55 to +125 c storage temperature range ?50 to +150 c (1) stresses above these ratings may cause permanent damage. exposure to absolute maximum conditions for extended periods may degrade device reliability. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. 2 submit documentation feedback www .ti.com
electrical characteristics ads1225 ads1226 sbas346 ? may 2006 all specifications at t a = ?40 c to +105 c, avdd = +5v, dvdd = +3v, and v ref = +5v, unless otherwise noted. ads1225, ads1226 parameter test conditions min typ max unit analog input full-scale input voltage ainp ? ainn v ref v buffer off; ainp, ainn with respect to gnd gnd ? 0.1 avdd + 0.1 v absolute input voltage buffer on; ainp, ainn with respect to gnd gnd + 0.05 avdd ? 1.5 v buffer off 2 m w differential input impedance buffer on 1 g w common-mode input impedance buffer off 4 m w system performance resolution 24 bits high-speed mode 75 100 125 sps (1) data rate high-resolution mode 12 16 22 sps (1) integral nonlinearity (inl) end-point fit 0.0005 0.0020 % of fsr (2) offset error 60 200 m v offset error drift 0.3 m v/ c gain error 0.004 0.025 % gain error drift 0.3 ppm/ c common-mode rejection at dc 85 95 db analog power-supply rejection at dc, 10% d in avdd 95 db digital power-supply rejection at dc, dvdd = 2.7v to 5.5v 80 db ppm of fsr, high-speed mode 1.5 rms noise ppm of fsr, high-resolution mode 0.4 rms temperature sensor temperature sensor voltage t a = +25 c 106 mv temperature sensor coefficient 360 m v/ c voltage reference input reference input voltage v ref = vrefp ? vrefn 0.5 5 avdd v negative reference input gnd - 0.1 vrefp ? 0.5 v positive reference input vrefn + 0.5 avdd + 0.1 v voltage reference impedance 1.5 m w (1) sps = samples per second. (2) fsr = full-scale range = 2 v ref . 3 submit documentation feedback www .ti.com
ads1225 ads1226 sbas346 ? may 2006 electrical characteristics (continued) all specifications at t a = ?40 c to +105 c, avdd = +5v, dvdd = +3v, and v ref = +5v, unless otherwise noted. ads1225, ads1226 parameter test conditions min typ max unit digital input/output v ih 0.8 dvdd dvdd + 0.1 v v il gnd ? 0.1 0.2 dvdd v logic levels v oh i oh = 1ma 0.8 dvdd v v ol i ol = 1ma 0.2 dvdd v input leakage 10 m a power supply avdd 2.7 5.5 v dvdd 2.7 5.5 v shutdown < 1 m a avdd = 5v, converting, buffer off 285 m a avdd current avdd = 5v, converting, buffer on 405 m a avdd = 3v, converting, buffer off 265 m a avdd = 3v, converting, buffer on 385 m a shutdown < 1 m a dvdd current dvdd = 5v, converting 90 m a dvdd = 3v, converting 55 m a avdd = 5v, dvdd = 3v, buffer off 1.6 2.5 mw total power dissipation avdd = dvdd = 3v, buffer off 1 mw temperature range specified ?40 +105 c operating ?55 +125 c storage ?60 +150 c 4 submit documentation feedback www .ti.com
pin configuration ads1225 ads1226 sbas346 ? may 2006 pin descriptions ? ads1225 terminal analog/digital name no. input/output description start 1 digital input high: start conversions; low: shutdown sclk 2 digital input serial clock input dual-purpose output: drdy/dout 3 digital output data ready: indicates valid data by going low. data output: outputs data, msb first, on the rising edge of sclk. bufen 4 digital input enables buffer after mux gnd 5 ground ground tempen 6 digital input selects temperature sensor input from mux mode 7 digital input selects between high-speed and high-resolution modes nc 8 no connect nc 9 no connect ainp1 10 analog input analog channel 1 positive input ainn1 11 analog input analog channel 1 negative input gnd 12 ground analog and digital ground vrefn 13 analog input negative reference input vrefp 14 analog input positive reference input avdd 15 analog analog power supply dvdd 16 digital digital power supply 5 submit documentation feedback www .ti.com rgv package qfn-16 4.0mm x 4.0mm (top view) start sclk drdy/dout bufen gndainn1 ainp1 nc dvdd avdd vrefp vrefn 12 3 4 12 11 10 9 ads1225 16 15 14 13 gnd tempen mode nc 5 6 7 8
ads1225 ads1226 sbas346 ? may 2006 pin descriptions ? ads1226 terminal analog/digital name no. input/output description start 1 digital input high: start conversions; low: shutdown sclk 2 digital input serial clock input dual-purpose output: drdy/dout 3 digital output data ready: indicates valid data by going low. data output: outputs data, msb first, on the rising edge of sclk. bufen 4 digital input enables buffer after mux mux 5 digital input selects analog input from mux tempen 6 digital input selects temperature sensor input from mux mode 7 digital input selects between high-speed and high-resolution modes ainp2 8 analog input analog channel 2 positive input ainn2 9 analog input analog channel 2 negative input ainp1 10 analog input analog channel 1 positive input ainn1 11 analog input analog channel 1 negative input gnd 12 ground analog and digital ground vrefn 13 analog input negative reference input vrefp 14 analog input positive reference input avdd 15 analog analog power supply dvdd 16 digital digital power supply 6 submit documentation feedback www .ti.com start sclk drdy/dout bufen gndainn1 ainp1 ainn2 dvdd avdd vrefp vrefn 12 3 4 12 11 10 9 ads1226 16 15 14 13 mux tempen mode ainp2 5 6 7 8 rgv package qfn-16 4.0mm x 4.0mm (top view)
typical characteristics ads1225 ads1226 sbas346 ? may 2006 at t a = ?40 c to +85 c, avdd = +5v, dvdd = +3v, and v ref = +5v, unless otherwise noted. analog current vs temperature analog current vs temperature figure 1. figure 2. digital current vs temperature analog current vs supply voltage figure 3. figure 4. digital current vs supply voltage temperature sensor voltage vs temperature figure 5. figure 6. 7 submit documentation feedback www .ti.com avdd = 3v avdd = 5v buffer on current ( a) m 500450 400 350 300 temperature ( c) 0 - 25 25 50 75 125 - 50 100 temperature ( c) current ( a) m 350325 300 275 250 225 200 0 - 25 25 50 75 125 - 50 100 avdd = 3v avdd = 5v buffer off temperature ( c) current ( a) m 120105 9075 60 45 30 5 - 25 35 65 95 125 - 55 avdd = 5v avdd = 3v avdd supply voltage (v) current ( a) m 3.5 3.0 4.0 4.5 5.0 5.5 2.5 450400 350 300 250 200 buffer off buffer on dvdd supply voltage (v) current ( m a) 110100 9080 70 60 50 40 5.5 2.5 3.0 3.5 4.0 4.5 5.0 temperature ( c) temperature sensor voltage (mv) 5 - 25 35 65 95 125 - 55 150140 130 120 110 100 9080 70
ads1225 ads1226 sbas346 ? may 2006 typical characteristics (continued) at t a = ?40 c to +85 c, avdd = +5v, dvdd = +3v, and v ref = +5v, unless otherwise noted. integral nonlinearity vs input voltage integral nonlinearity vs input voltage figure 7. figure 8. offset vs temperature gain error vs temperature figure 9. figure 10. noise vs input voltage noise vs input voltage figure 11. figure 12. 8 submit documentation feedback www .ti.com input voltage, v (v) in noise (ppm of fsr, rms) - 3.5 - 2.5 - 1.5 - 0.5 0.5 1.5 2.5 3.5 3.02.5 2.0 1.5 1.0 0.5 0 high-speed modebuffer on input voltage, v (v) in - 3 - 4 - 2 - 1 0 1 2 3 4 5 - 5 1510 50 - 5 - 10 - 15 inl (ppm of fsr) - 10 c - 40 c +25 c +105 c +85 c +55 c buffer off - 2.5 3.5 - 3.5 input voltage, v (v) in 10 86 4 2 0 - 2 - 4 - 6 - 8 - 10 inl (ppm of fsr) - 1.5 - 0.5 0.5 1.5 2.5 buffer on - 40 c +25 c +105 c +85 c +55 c - 10 c gain error (%) 0.0020.001 0 - 0.001 - 0.002 temperature ( c) 0 - 25 25 50 75 125 - 50 100 temperature ( c) offset ( v) m 2010 0 - 10 - 20 - 30 - 40 - 25 0 125 - 50 25 50 75 100 input voltage, v (v) in noise (ppm of fsr, rms) 5 - 5 - 4 - 3 - 2 - 1 0 1 2 3 4 3.53.0 2.5 2.0 1.5 1.0 0.5 0 high-speed modebuffer off
ads1225 ads1226 sbas346 ? may 2006 typical characteristics (continued) at t a = ?40 c to +85 c, avdd = +5v, dvdd = +3v, and v ref = +5v, unless otherwise noted. noise vs input voltage noise vs input voltage figure 13. figure 14. noise histogram noise histogram figure 15. figure 16. high-speed mode data rate high-resolution mode data rate vs temperature vs temperature figure 17. figure 18. 9 submit documentation feedback www .ti.com input voltage, v in (v) noise (ppm of fsr, rms) 5 - 5 - 4 - 3 - 2 - 1 0 1 2 3 4 0.90.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 high-resolution modebuffer off input voltage, v (v) in noise (ppm of fsr, rms) - 3.5 - 2.5 - 1.5 - 0.5 0.5 1.5 2.5 3.5 0.70.6 0.5 0.4 0.3 0.2 0.1 0 high-resolution modebuffer on output code occurrence - 10 - 15 - 5 - 20 - 25 5 0 10 15 20 30 25 - 30 8070 60 50 40 30 20 10 0 high-resolution mode high-speed mode output code - 160 - 120 - 80 - 40 0 40 80 120 160 occurrence 250200 150 100 50 0 temperature ( c) data period (sps) 120110 100 9080 70 0 - 25 25 50 75 125 - 50 100 temperature ( c) data period (sps) 2118 15 12 0 - 25 25 50 75 125 - 50 100
overview analog inputs (ainx+, ainx?) ads1225 ads1226 sbas346 ? may 2006 the ads1225 and ads1226 are 24-bit delta-sigma the input signal to be measured is applied to the a/d converters. figure 19 shows a conceptual input pins ainpx and ainnx. the positive internal diagram of the device. the ads1225 has a single input is generalized as ainp, and the negative channel, while the ads1226 allows for one of two internal input is generalized as ainn. the signal is input channels to be selected through a multiplexer. selected though the input mux, which is controlled a buffer can also be selected to increase the input by mux, as shown in table 1 . the ads1225 and impedance. the modulator measures the differential ads1226 accept differential input signals, but can input signal v in = (ainp ? ainn) against the also measure unipolar signals. when measuring differential reference v ref = (vrefp ? vrefn). the unipolar (or single-ended) signals with respect to full-scale input range is v ref . a 2-wire serial ground, connect the negative input (ainn) to ground interface indicates conversion completion and and connect the input signal to the positive input provides the user with the output data. an internal (ainp). note that when the ads1225 and ads1226 oscillator allows for free-running of the ads1225 and are configured this way, only half of the converter ads1226. full-scale range is used since only positive digital output codes are produced. an input buffer can be two other pins are used to control the operation of selected to increase the input impedance of the a/d the ads1225 and ads1226. the start pin initiates converter with the bufen pin. conversions. the mode pin puts the device into one of two modes. in high-speed mode, the device gives table 1. input channel selection with mux data at 100 samples per second (sps). in digital pin selected analog inputs high-resolution mode, data comes out at 16sps with lower noise. in both modes, the device has mux positive input negative input single-cycle settling, reducing the latency of the 0 ainp1 ainn1 output data. 1 ainp2 ainn2 figure 19. conceptual diagram of the ads1225 and ads1226 10 submit documentation feedback www .ti.com mux serial interface oscillator ds adc vrefp vrefn buffer mux ads1226 only ainp1 ainn1 ainpainn ainp2 ainn2 drdy/dout sclk tempen start mode bufen v in s s v ref
analog input measurement without the input analog input measurement with the input buffer ads1225 ads1226 sbas346 ? may 2006 buffer with the buffer disabled by setting the bufen pin low, the ads1225 and ads1226 measure the input signal using internal capacitors that are continuously charged and discharged. figure 20 shows a simplified schematic of the ads1225/6 input circuitry, with figure 21 showing the on/off timings of the switches. the s 1 switches close during the input sampling phase. with s 1 closed, c a1 charges to ainp, c a2 charges to ainn, and c b charges to (ainp ? ainn). for the discharge phase, s 1 opens figure 22. effective analog input impedances first and then s 2 closes. c a1 and c a2 discharge to with the buffer off approximately vdd/2 and c b discharges to 0v. the constant charging of the input capacitors presents a load on the inputs that can be represented by esd silicon diodes protect the inputs. to keep these effective impedances. figure 22 shows the input diodes from turning on, make sure the voltages on circuitry with the capacitors and switches of the input pins do not go below gnd by more than figure 20 by their effective impedances. 100mv, and likewise do not exceed vdd by 100mv. this limitation is shown in equation 1 : (1) when the buffer is enabled by setting the bufen pin high, a low-drift, chopper-stabilized input buffer is used to achieve very high input impedance. the buffer charges the input sampling capacitors, thus removing the load from the measurement. because the input buffer is chopper-stabilized, the charging of parasitic capacitances causes the charge to be carried away, as if by resistance. the input impedance can be modeled by a single resistor, as shown in figure 23 . figure 20. simplified input structure with the buffer turned off figure 23. effective analog input impedances with the buffer on note that the analog inputs (listed in the electrical figure 21. s 1 and s 2 switch timing for figure 20 characteristics table as absolute input range) must remain between gnd + 0.05v to avdd ? 1.5v. exceeding this range degrades linearity and results in performance outside the specified limits. 11 submit documentation feedback www .ti.com zeff = t /c a sample a1 = 4m w zeff = t /c b sample b = 2m w zeff = t /c a sample a2 = 4m w ainpx ainnx avdd/2 avdd/2 gnd 100mv ( ainp, ainn ) vdd 100mv mux avdd avdd/2 avdd/2 s 1 s 1 ainn ainp s 2 c a1 3pfc b 6pfc a2 3pf avdd esd protection ainpx ainnx s 2 ainp ainn 1g w on off on s 1 s 2 off t = 12 s m sample
temperature sensor voltage reference inputs ads1225 ads1226 sbas346 ? may 2006 (vrefp, vrefn) internal diodes provide temperature-sensing capability. by setting the tempen pin high, the the voltage reference used by the modulator is selected analog inputs are disconnected and the generated from the voltage difference between inputs to the a/d converter are connected to the vrefp and vrefn: v ref = vrefp ? vrefn. the anodes of two diodes scaled to 1x and 64x in current reference inputs use a structure similar to that of the and size inside the mux, as shown in figure 24 . by analog inputs. a simplified diagram of the circuitry on measuring the difference in voltage of these diodes, the reference inputs is shown in figure 25 . the temperature changes can be inferred from a baseline switches and capacitors can be modeled with an temperature. typically, the difference in diode effective impedance of 250k w . voltages is 106mv at +25 c, with a temperature coefficient of 360 m v/ c. a similar structure is used in the msc1210 for temperature measurement. for more information, see ti application report sbaa100 , using the msc121x as a high-precision intelligent temperature sensor , available for download at www.ti.com . figure 25. simplified reference input circuitry esd diodes protect the reference inputs. to prevent these diodes from turning on, make sure the voltages on the reference pins do not go below gnd by more than 100mv, and likewise, do not exceed vdd by 100mv. this limitation is shown in equation 2 : (2) for best performance, bypass the voltage reference inputs with a 0.1 m f capacitor between vrefp and vrefn. place the capacitor as close as possible to the pins. figure 24. measurement of the temperature sensor in the input the differential voltage reference inputs and the wide range of operation (v ref can support up to avdd) make ratiometric measurements easy to implement. 12 submit documentation feedback www .ti.com avdd zeff = 500k w vrefp vrefn avdd esd protection 16pf gnd 100mv ( vrefp, vrefn ) vdd 100mv ainp ainp1 ainn1 ainp2 ainn2 8i 1i 1x 8x ainn tempen avdd mux
internal oscillator mode data ready/data output ( drdy/dout) start serial clock input (sclk) ads1225 ads1226 sbas346 ? may 2006 the ads1225 and ads1226 have an internal the ads1225 and ads1226 have two modes of oscillator and run without an external crystal or operation, allowing for high-speed or oscillator. high-resolution. by taking the mode pin high, the data rate is approximately 100hz with an rms noise of 15 m v. when the mode pin is low, the ads1225 and ads1226 average multiple samples to increase this digital output pin serves two purposes. first, it the noise performance to 4 m v of rms noise with a indicates when new data is ready by going low. data rate of 16hz. table 2 shows the mode pin afterwards, on the first rising edge of sclk, the operation. drdy/dout pin changes function and begins to output the conversion data, most significant bit table 2. mode pin operation for the ads1225 (msb) first. data is shifted out on each subsequent and ads1226 sclk rising edge. after all 24 bits have been mode pin mode data rate noise retrieved, the pin can be forced high with an 0 high-resolution 16sps 4 m vrms additional sclk. it then stays high until new data is ready. this configuration is useful when polling on 1 high-speed 100sps 15 m vrms the status of drdy/dout to determine when to begin data retrieval. the start pin provides easy and precise control of conversions. pulse the start pin high to begin a this digital input shifts serial data out with each conversion as shown in figure 26 and table 3 . the rising edge. as with clk, this input may be driven completion of the conversion is indicated by the with 5v logic regardless of the dvdd voltage. there drdy/dout pin going low. once the conversion is hysteresis built into this input, but care should still completes, the ads1225 and ads1226 be taken to ensure a clean signal. glitches or automatically shut down to save power. they stay slow-rising signals can cause unwanted additional shut down until start is once again taken high to shifting. for this reason, it is best to make sure the begin a new conversion. rise-and-fall times of sclk are less than 50ns. figure 26. controlling conversion with the start pin table 3. start pin conversion times for figure 26 symbol description min max units t start minimum start pulse to initiate a conversion 17 m s t conv conversion time high-speed mode 8.0 13.3 ms conversion time high-resolution mode 45.5 83.3 ms 13 submit documentation feedback www .ti.com drdy/dout start sclk ads1225/6 status shutdown conversion data converting t conv t start
data format ads1225 ads1226 sbas346 ? may 2006 table 4. ideal output code vs input signal the ads1225 and ads1226 can be configured to continuously convert by holding the start pin high input signal v in as shown in figure 27 . with start held high, a new (ainp - ainn) ideal output code ( (1) ) conversion starts immediately after the previous 3 +v ref 7fffffh conversion completes. this configuration continues until the start pin is taken low. 000001h 0 000000h the ads1225 and ads1226 output 24 bits of data in ffffffh binary two's complement format. the least significant bit (lsb) has a weight of (v ref )/(2 23 ? 1). the positive full-scale input produces an output code of 7fffffh 800000h and the negative full-scale input produces an output code of 800000h. the output clips at these codes for signals exceeding full-scale. table 4 summarizes the ideal output codes for different input signals. (1) excludes effects of noise, inl, offset, and gain errors. figure 27. conversion with the start pin tied high 14 submit documentation feedback www .ti.com v ref 2 23 1 v ref 2 23 1 v ref 2 23 2 23 1 drdy/dout start ads1225/6 status sclk held low in this example. data ready data ready converting converting converting converting
data retrieval ads1225 ads1226 sbas346 ? may 2006 avoid data retrieval during the update period. drdy/dout remain at the state of the last bit with the start pin high, the ads1225 and shifted out until it is taken high (see t 6 ), indicating ads1226 continuously convert the analog input that new data is being updated. to avoid having signal. to retrieve data, wait until drdy/dout goes drdy/dout remain in the state of the last bit, shift low, as illustrated in figure 28 and table 5 . after this a 25th sclk to force drdy/dout high (refer to occurs, begin shifting out the data by applying figure 29 ). this technique is useful when a host sclks. data is shifted out msb first. it is not controlling the ads1225 and ads1226 is polling required to shift out all 24 bits of data, but the data drdy/dout to determine when data is ready. must be retrieved before the new data is updated (see t 2 ) or else it will be overwritten. figure 28. data retrieval timing table 5. data retrieval times for figure 28 symbol description min max units t ds drdy/dout low to first sclk rising edge 0 ns t sclk sclk positive or negative pulse width 100 ns t pd sclk rising edge to new data bit valid: propagation delay 50 ns t hd sclk rising edge to old data bit valid: hold time 0 ns t up data updating: no readback allowed 29.5 49.2 m s t conv conversion time (1/data rate), high-speed mode 8.0 13.3 ms conversion time (1/data rate), high-resolution mode 45.5 83.3 ms figure 29. data retrieval with drdy/dout forced high afterwards 15 submit documentation feedback www .ti.com drdy/dout 23 22 21 1 24 0 lsb msb data data ready sclk start tied high t ds t conv t sclk t sclk t up new data ready t pd t hd 23 1 24 25 22 21 0 data 25th sclk to force /dout high drdy data ready new data ready drdy/dout sclk
self-calibration ads1225 ads1226 sbas346 ? may 2006 when the calibration is complete, drdy/dout goes low, indicating that new data is ready. there is no self-calibration can be initiated at any time, although need to alter the analog input signal applied to the in many applications the ads1225 and ads1226 ads1225 and ads1226 during calibration; the input drift performance is so good that the self-calibration pins are disconnected within the a/d converter and performed automatically at power-up is all that is the appropriate signals are applied internally and needed. to initiate self-calibration, apply at least two automatically. the first conversion after a calibration additional sclks after retrieving 24 bits of data. is fully settled and valid for use. the time required for figure 30 and table 6 illustrate the timing pattern. a calibration depends on two independent signals: the 25th sclk will send drdy/dout high. the the falling edge of sclk and an internal clock falling edge of the 26th sclk will begin the derived from clk. variations in the internal calibration cycle. additional sclk pulses may be calibration values change the time required for sent after the 26th sclk; however, activity on sclk calibration (t 8 ) within the range given by the min/max should be minimized during calibration for best specs. t 11 and t 12 described in the next section are results. affected likewise. figure 30. self-calibration timing table 6. self-calibration time for figure 30 symbol description min max units t cal first data ready after calibration 187 313 ms 16 submit documentation feedback www .ti.com 23 drdy/dout sclk 1 24 t cal 25 26 23 22 21 0 data ready after calibration calibration begins
application information general recommendations ads1225 ads1226 sbas346 ? may 2006 pay special attention to the reference and analog inputs. these inputs are critical to performance. bypass the voltage reference using similar the ads1225 and ads1226 are high-resolution a/d techniques to the supply voltages. the quality of the converters. achieving optimal device performance reference directly affects the overall accuracy of the requires careful attention to the support circuitry and device. make sure to use a low noise and low drift printed circuit board (pcb) design. figure 31 shows reference such as the ref1004 . often, only a simple the basic connections for the ads1225 and rc filter is needed on the inputs. the circuit limits ads1226. as with any precision circuit, be sure to the higher frequency noise. avoid low-grade use good supply bypassing capacitor techniques. a dielectrics for the capacitors and place them as close smaller value ceramic capacitor in parallel with a as possible to the input pins. keep the traces to the larger value tantalum capacitor works well. place the input pins short, and carefully watch how they are capacitors, in particular the ceramic ones, close to routed on the pcb. the supply pins. use a ground plane and tie the ads1225 and ads1226 gnd pin and bypass after the power supplies and reference voltage have capacitors directly to it. avoid ringing on the digital stabilized, issue a self-calibration command to inputs. small resistors ( ? 100 w ) in series with the minimize offset and gain errors. digital pins can help by controlling the trace impedance. place these resistors at the source end. figure 31. basic connections 17 submit documentation feedback www .ti.com ads1226 start sclk drdy/dout bufen gnd ainn1 ainp1 ainn2 12 3 4 1211 10 9 100 w 100 w 100 w 100 w 100 w 100 w 100 w same as shownfor ainp1 and ainn1. 10 f m 16 15 avdd dvdd vrefp vrefn tempen mux mode ainp2 0.1 f m 0.1 f m +5v +3v 10 f m 14 13 5 6 7 8 0.1 f m ref1004 301 w 220pf 0.1 f m 220pf 301 w
small input signals ads1225 ads1226 sbas346 ? may 2006 measurement of approximately 1v while keeping the noise contribution of the opa2333 low. the noise is figure 32 shows the schematic of the ads1225 for low enough compared to full-scale to create a measuring small output signals such as the output of several-thousand count weigh scale, even in a bridge sensor or load cell. in this application, the high-speed mode. for better accuracy, this noise load cell is combined with the ads1225 and an could be lowered through either additional filtering or msp430 microcontroller. an opa2333 is used to using the high-resolution mode. buffer the inputs and to provide the gain of the load cell signal. a 5v source is used as the reference and it is important to make sure that the reference and the excitation, although any clean source can create inputs are clean from clocks or other periodic signals a proper ratiometric signal for the reference. to prevent coupling. isolate the analog from the digital supplies and grounds whenever possible. a typical load cell with a bridge sensitivity of 2mv/v using a 5v source would have a full-scale output of 10mv. the recommended gain of the opa2333, for this load cell using low-drift resistors, would be 1 + 2r f /r g = 100.8v/v. this value gives a full-scale figure 32. using the opa2333 as a gain stage in front of the ads1225 18 submit documentation feedback www .ti.com ads1225 vrefpvrefn start drdy /dout avdd dvdd gnd ainp1 msp430xxx or c m gnd +5v +5v +5v r f 4.99k w r f 4.99k w r g 100 w 0.22 f m 1k w 10 f m 0.1 f m 0.1 f m load cell ainn1 1k w +3v +3v 0.1 f m 0.1 f m 0.1 f m sclk 1/2 opa2333 1/2 opa2333 g = 1 + 2r f r g mode tempen bufen use low-drift resistors for r and r f g
large input signals ads1225 ads1226 sbas346 ? may 2006 figure 33 shows a basic schematic. the negative input of the ina159 is grounded while the positive many industrial applications require measurement of input is allowed to swing from ?10v to +10v. signals that go beyond 5v. the ads1225 can be similarly, the negative input of the ads1225 is used to measure large input signals with the help of grounded while the positive input swings from 0.5v an ina159. the precision, level translation to +4.5v given the useful v out swing of the ina159. differential amplifier converts a 10v input to a 5v the larger signal is easily measured without the input scale. this design allows systems to be run need for extra 10v supplies. see the ina159 data from a single 5v supply without the need for higher sheet for additional details. voltage supplies for signal conditioning. figure 33. with the help of an ina159, the ads1225 measures 10v signals 19 submit documentation feedback www .ti.com 20k w 100k w 40k w 100k w 40k w v+v - senseref 2 ref 1 +in - in ina159 v 10v in out ads1225 vrefpvrefn start drdy /dout avdd dvdd gnd ainp1 msp430xxx or c m gnd +5v +5v 10 f m 0.1 f m 0.1 f m ainn1 +3v +3v 0.1 f m 1 f m sclk mode tempen bufen 1k w
ads1225 ads1226 sbas346 ? may 2006 figure 34. summary of serial interface waveforms table 7. digital pin operations input digital pin pin no. 0 1 start 1 shutdown mode start conversion bufen 4 buffer off buffer on mux (ads1226 only) 5 ainp1 ? ainn1 input ainp2 ? ainn2 input tempen 6 temperature sensor off temperature sensor on mode 7 high-resolution mode high-speed mode 20 submit documentation feedback www .ti.com drdy/dout sclk start tied high sclk start tied high start tied high 23 22 21 0 msb lsb 1 24 drdy/dout 23 22 21 0 1 24 25 drdy/dout sclk data ready after calibration 23 22 21 0 1 24 25 26 begin calibration (a) data retrieval (b) data retrieval with /dout forced high afterwards drdy (c) self-calibration (d) single conversions with start pulse drdy/dout start sclk 22 21 20 23 1
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) ADS1225IRGVR active qfn rgv 16 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year ADS1225IRGVRg4 active qfn rgv 16 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year ads1225irgvt active qfn rgv 16 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year ads1225irgvtg4 active qfn rgv 16 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year ads1226irgvr active qfn rgv 16 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year ads1226irgvrg4 active qfn rgv 16 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year ads1226irgvt active qfn rgv 16 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year ads1226irgvtg4 active qfn rgv 16 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 20-sep-2006 addendum-page 1

important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security low power wireless www.ti.com/lpw telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2006, texas instruments incorporated

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